Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining.
Many pipelined processors, especially those used in the embedded market, are relatively simple single-threaded in-order machines. As a result, they are subject to control, structural, and data hazard stalls. More complex processors are typically multi-threaded processors that have out-of-order execution pipelines. These more complex processors schedule execution of instructions around hazards that would stall an in-order machine.
What is needed are techniques, apparatuses and methods for interfacing processors having out-of-order execution pipelines to coprocessors having in-order execution pipelines.